At the heart of telecommunications switches and network routers is a switching fabric that is often constructed from one or more crossbar switches. Such switches forward packets between input ports and output ports in network routers and connect circuits from input ports to output ports in telecommunications switches.
In the past, high-speed switches, over 1 Gb/s per port of bandwidth, were typically implemented in bipolar or GaAs technology. While this fast circuit technology enabled construction of a fast crossbar switch, this technology is expensive and does not permit the integration of CMOS logic functions on the same chip with the switch.
Most CMOS crossbar switches use static gate circuits to implement each crosspoint. Tri-state inverters may be employed to selectively gate inputs onto an output bus, or, alternatively, a multiplexer constructed from CMOS gates may be used at each output to select the active input. While these circuits are simple and robust, they also require considerable chip area, dissipate large amounts of power, and have limited scalability. A conventional crossbar of this type is described, for example, in U.S. Pat. No. 4,914,429.
An improved CMOS crossbar switch design was reported by Shin and Hodges (Shin and Hodges, A 250-Mbit/s CMOS Crosspoint Switch, JSSC 28(2), April 1989, pp. 478–486). Their switch employs a static CMOS inverter for a crosspoint but improves efficiency by reducing the swing of the column (output) line of the switch using a CMOS inverter with resistive feedback. While an improvement, this switch requires large tri-state inverters at the crosspoints. This type of switch circuit still dissipates large amounts of power, takes significant area, and has limited scalability.